1. Field of the Invention
The present invention relates to the fabrication of integrated circuits, and more particularly to a cleaning process and system which substantially reduces the metallic, particle and organic contamination of integrated circuit wafers during planar processing.
2. Description of the Prior Art
For the past 25 years, a huge research and development effort has been directed to the production of integrated circuits. Much of this effort has been directed to the development of the planar process, in which integrated circuit devices are produced using a sequence of steps carried out on the surface of a semiconductor wafer. More particularly, the planar process involves the proper sequencing and repetition of the steps of oxidation, patterning, dopant-addition and dopant diffusion, which results in the selective introduction of p- and n-type dopant atoms into specific regions on the surface of the wafer. The introduction of the dopant atoms into specific regions of the wafer surface is the basis for the formation of active and passive devices having ever decreasing dimensions.
From a processing standpoint, the key steps in the planar process are: 1) the formation of a masking oxide layer; 2) the selective removal or etching of the oxide layer; 3) the deposition of the dopant atoms on or near the wafer surface; and 4) the diffusion of the dopant atoms into the wafer surface. As described below, many of these steps are performed as "wet" processes, so called because the steps involve immersing the wafer in various acids and other solutions. In addition, there are typically a number of cleaning steps performed between the key steps, with these cleaning steps also being wet processes.
The following discussion focuses on the planar processing of silicon integrated circuits, however, similar processing steps are used for gallium arsenide and other semiconductor materials. Two important advantages of silicon are its good semiconducting properties (i.e., its intrinsic-carrier concentration versus dopant density), and the ability to form on it a stable, controllable silicon dioxide film that has excellent chemical properties. Indeed, the chemical properties of the silicon-silicon dioxide system allow for the selective etching of the silicon and the oxide, and for the doping of specific regions of the silicon. Both of these chemical properties are key to producing dense arrays of semiconductor devices on a single wafer.
The first step in producing silicon integrated circuits is the production of large, high quality silicon crystals. The crystals must also be of very high-purity; typically only about one unintentional, electrically active impurity atom pure billion silicon atoms can be tolerated. The crystals are initially formed from silicon dioxide and carbon in a high temperature (about 2000 degrees Centigrade) electric arc furnace, which produces a metallurgical-grade silicon. This metallurgical-grade silicon is then converted to trichlorosilane which is, in turn, reduced by hydrogen to form high-purity, polysilicon semiconductor-grade silicon.
The semiconductor-grade silicon is then formed into a large, nearly perfect single crystal using either the Czochralski (CZ) method or the float-zone (FZ) method. The CZ method involves melting the polysilicon in a fused-silica crucible in an inert gas atmosphere (such as argon), then inserting a high-quality seed crystal in the melt. The seed is slowly pulled from the melt while rotating, thus producing a large, single crystal ingot of silicon. By contrast, in the FZ method a rod of cast polycrystalline silicon is held in a vertical position and slowly rotated while a melted region is slowly passed from the bottom of the rod to the top.
Once the single silicon crystal has been grown, it is sliced with a diamond saw into thin wafers. Each wafer is then polished and chemically etched until a mirror-like surface is obtained. Marks may also added to the edge of the wafer to indicate the orientation of the crystal structure. After the wafers have been formed and polished, the actual planar process begins.
The first step of the planar process is the growth of an oxide layer of about 20 nanometers to 1 micrometer in thickness on the surface of the wafer. The oxide layer is typically grown either by thermal oxidation or deposition, with thermally grown oxides generally of a higher quality than deposited oxides. In order to maintain the stability of the electrical properties of the interface between the silicon and the oxide, the numbers of organic or metallic on the surface and in the oxide impurities must be kept to a minimum.
The thermal oxide is formed by placing the wafer inside a resistance-heated furnace having a temperature in the range of 850 to 1100 degrees Centigrade. The oxidizing agent can be dry oxygen or it can contain water vapor, with oxidation proceeding more rapidly in the latter environment. Since oxidation takes place at the silicon-silicon dioxide interface, the oxidizing agent must diffuse through any previously formed oxide and then react with the silicon surface. In fact, for lower temperatures and thinner oxides, the oxide thickness is a linear function of the oxidation time. However, at higher temperatures and for thicker oxides, the oxide thickness is proportional to the square root of the oxidation time. This provides a practical upper limit on the thickness of oxides which can be obtained.
After the oxide layer has been formed, the second step of the planar process involves the selective etching of the oxide is performed to expose areas of the silicon where dopant atoms are to be introduced. The selective removal is accomplished using a light-sensitive polymer material called a resist, in a process called photolithography. The oxidized wafer is lightly coated with the liquid resist and then the resist is dried. A partially transparent photomask is then placed on the wafer and aligned using a microscope. The wafer is then exposed to ultraviolet light, which changes the chemical structure of the portions of the resist which are not shielded by the photomask. Finally, the exposed portions of the resist are then selectively dissolved using a solvent such as trichloroethylene.
Note that as the minimum feature size of semiconductor devices approaches the wavelength of the ultraviolet light, diffraction can limit the available resolution when using conventional photoplithography. In order to overcome this limitation, alternatives to conventional photolithography have been developed. Two of these advanced approaches are electron-beam lithography and x-ray lithography, the latter in which the greatest progress has been made to date.
Electron-beam lithography uses a focused stream of electrons to deliver exposure energy to the resist. More particularly, the electron beam is deflected to expose the desired pattern sequentially, so that a mask is not needed. In order to control the deflection, the information needed to deflect the electron beam is stored in a computer. Additionally, the electron beam can be finely focused to a size much smaller than the minimum feature size an moved across the surface of the wafer, or the beam can be formed into a rectangular shape and the pattern built up by repeated block-like exposures.
After the photomask pattern has been formed in the resist, the unprotected portions of the oxide are chemically etched to transfer the pattern to the silicon wafer. The chemical etching may be accomplished by dissolving the unprotected portions of the oxide using hydrofluoric acid, resulting in the exposure of corresponding portions of the silicon wafer. The resist is then removed from the remaining portions of the oxide by "ashing", in which the resist is burned off in a plasma chamber under vacuum.
Once the remaining portions of the resist have been removed, the dopant atoms are added to the exposed portions of the silicon wafer. The resulting dopant profile, or distribution of dopant atoms, is primarily determined by steps three and four of the planar process. In step three, the dopant atoms are placed on or near the surface of the wafer by liquid coating, ion implantation or gaseous deposition. The fourth step involves transporting the dopant atoms into the wafer using a process called drive-in diffusion. Note that the shape of the resulting dopant distribution is determined by the method of dopant placement, while the diffusion depth depends primarily on the temperature and time of the drive-in diffusion.
A major concern throughout the planar fabrication process is in eliminating contamination. Specifically, the current goal of modem integrated circuit processing is to produce wafers having less than four particles of contamination per wafer, with each particle being less than 0.5 micron in diameter. Of particular concern is the fine organic ash that remains on the wafer surface following conventional or electron-beam photolithography and ashing.
Following the lithography and ashing steps, the wafer is cleaned using the following conventional cleaning process. First, a hot sulfuric acid/hydrogen peroxide wash is used to remove organic contamination. The hot sulfuric acid/hydrogen peroxide wash is followed by an ammonium hydroxide/hydrogen peroxide rinse to remove non-metallic particles, and then a hydrochloric acid/hydrogen peroxide rinse to remove any metallic particles introduced by the high ph (approximately 12) of the ammonium hydroxide/hydrogen peroxide rinse.
In the conventional cleaning process, the hot sulfuric acid/hydrogen peroxide wash is performed at a temperature of between 120 and 160 degrees Centigrade in a special quartz vessel. However, quartz is extremely fragile and is subject to very high internal stress during fabrication which limits its service life, particularly under ultrasonic vibration. Yet ultrasonic vibration may be required to completely remove the contamination remaining on the wafer surface following ashing. Additionally, the inner surface of the quartz vessel may contain its own organic film which can find its way into the acid and eventually onto the wafers. Thus, the time required to remove these contaminants, coupled with the high cost and limited service life of the vessel, are important limiting factors in the throughput of the planar process.
Accordingly, there is a need for a method and apparatus for cleaning wafers during the production of integrated circuits which does not require the use of an expensive and fragile quartz vessel, which uses reduced concentrations of cleaning solvents, and in which ultrasonic vibrations are used to improve the efficiency and increase the throughput of the cleaning process.